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2. Having less set associativity for a shared cache than the number of cores or threads sharing that cache 3. Using average memory access time to evaluate the memory hierarchy of an out-of-order processor cache, allowing main memory to service the request quickly without incurring significant memory traffic. Thus, the Alloy Cache achieves fast tag lookup, reducing DRAM cache hit latency. However, by forgoing associativity, that work sacrifices DRAM cache hit rate for hit latency. Even though a set-associative DRAM cache design can set associative cache of capacity 8KB and 64 byte blocks, compute the overall miss rate (number of misses divided by number of references). Assume that all variables except array locations reside in registers, and that arrays A, B, and C are placed consecutively in memory. double A[1024], B[1024], C[1024]; for(int i=0;i<1000;i += 2)